ECE Department Calendar

Jul
3
Fri
Independence Day holiday (Observed)
Jul 3 all-day
Independence Day holiday (Observed)
Jul
4
Sat
Second Session Classes: Last day to drop (delete) classes
Jul 4 all-day
Second Session Classes: Last day to drop (delete) classes
Independence Day
Jul 4 – Jul 4 all-day
Jul
8
Wed
Second Session Classes: Last day to add, elect CR/NC, or audit classes
Jul 8 all-day
Second Session Classes: Last day to add, elect CR/NC, or audit classes
Jul
10
Fri
Shomit Das-PhD final thesis defense @ Warnock Engineering Building (WEB) Room 1450
Jul 10 @ 2:00 pm – 4:00 pm

UNIVERSITY OF UTAH
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT

DISSERTATION DEFENSE FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

by

Shomit Das
Advisor: Ken Stevens

Techniques for fast, energy efficient on-die global communication


Communication surpasses computation as the power and performance bottleneck in forthcoming exascale processors. Scaling has made transistors cheap, but on chip wires have grown more expensive, both in terms of latency as well as energy. Therefore, the need for low energy, high performance interconnects is highly pronounced, especially for long distance communication.
In this work, we examine two aspects of the global signaling problem. The first part of the thesis focuses on a high bandwidth asynchronous signaling protocol for long distance communication. Asynchrony among IP cores on a chip has become necessary in a System on Chip (SoC) environment. Traditional asynchronous handshaking protocol suffers from loss of throughput due to the added latency of sending the acknowledge signal back to the sender. We demonstrate a method that supports end-to-end communication across links with arbitrarily large latency, without limiting the bandwidth, so long as line variation can be reliably controlled. We also evaluate the energy and latency improvements as a result of the design choices made available by this protocol.
The use of transmission lines as a physical interconnect medium shows promise for deep submicron technologies. In our evaluations, we notice a lower energy footprint, as well as vastly reduced wire latency for transmission line interconnects. We approach this problem from two sides. Using field solvers, we investigate the physical design choices to determine the optimal way to implement these lines for a given back-end-of-line (BEOL) stack. We also approach the problem from a system designer’s viewpoint, looking at ways to optimize the lines for different performance targets. This work analyzes the advantages and pitfalls of implementing asynchronous channel protocols for communication over long distances. Finally, the innovations resulting from this work are applied to a network-on-chip design example and the resulting power-performance benefits are reported.


Friday July 10, 2015
2:00 PM
Warnock Engineering Building (WEB) Room 1450
The public is invited

Jul
17
Fri
Second Session Classes: Last day to withdraw from classes
Jul 17 all-day
Second Session Classes: Last day to withdraw from classes
Jul
24
Fri
Pioneer Day holiday
Jul 24 all-day
Pioneer Day holiday
Pioneer Day
Jul 24 – Jul 24 all-day
Jul
31
Fri
Last day to reverse CR/NC option
Jul 31 all-day
Last day to reverse CR/NC option
Second Session Classes: Last day to reverse CR/NC option
Jul 31 all-day
Last day to reverse CR/NC option