Nurunnaha Islam Mou MS thesis final defense

UNIVERSITY OF UTAH

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT

 

THESIS DEFENSE FOR THE DEGREE OF

MASTER OF SCIENCE

 

by

 

Nurunnahar Islam Mou

Advisor: Massood Tabib-Azar

                                                                                                                                                           

 

Experimental and simulation study of gate controlled resistive switching memories

 

Scaling limitation of current memory technology requires invention of new class of memory that has high density, fast programming and access time as well as good non-volatility. Memristors are good candidates for such application and researchers are investigating memristors vigorously now-a-days. Anticipated advantages of these devices are long retention time, high access speed, endurance, low power and high density. Memristors were first proposed theoretically as the fourth circuit element by L. Chua in 1971 but it did not came into practical implementation until 2008 when researchers in HP lab fabricated and recognized the first ever memristor. However, the research on memristor dates back to 1964.

            There are several significant contributions within the scope of this research work. This thesis work demonstrates the fabrication and operation principle of gate controlled resistive switching memory device. The fabricated gated memristors are among first of its kind. In-depth studies of the switching layers used in the fabricated gated memristors are also presented prior to the fabrication process. Firstly, two switching layers i. e. Cu2S and Ag2S are selected to be used in our devices. Using advanced characterization techniques such as Atomic Force Microscopy, growth of metallic conductive filaments are observed under voltage magnitude and polarity. Secondly, larger two terminal memristor (Au/Ag2-xS/W) was fabricated to study the time dependent switching behavior of Cu2S and Ag2S layers. This study was further extended to demonstrate the effects of illumination on the switching kinetics of the fabricated devices and it was found that the average switching time of these devices got significantly decreased under illumination.

            Third, a novel three terminal gated memristor was proposed and fabricated. The motivation for this work arises from the fact that we would like to tune the switching voltage of the memristors so that they can be used as sensors and/or integrated switches in non-volatile memory. The new recessed gate electrode introduced in this structure was able to guide the charged metallic ions depending on how much voltage was applied at the gate and either aid or inhibit the formation of the conductive filament. As a result, different turn-off voltage was observed for different gate voltages. These devices also exhibit very high sub-threshold slope which make them suitable as low power switches.

            Last but not the least; a numerical simulation model was developed to explain the gate electric field effect observed in our fabricated Pt/Cu2-xS/Pt based gated memristor. Through the simulation it was shown that, application of gate voltage results in bending and narrowing of the conductive metallic filament. The bending is away or towards the gate structure depending on the polarity of the gate voltage applied.

 

 

 

Friday January 29, 2016

10:00 AM

Sorenson Molecular Bioengineering Building (SMBB) Room 3750

The public is invited

William Lee PhD final defense

UNIVERSITY OF UTAH
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT

DISSERTATION DEFENSE FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

by

William Lee
Advisor: Ken Stevens

Achieving Backend Robustness for Timed Asynchronous Circuits

The design of integrated circuit (IC) requires an exhaustive verification and a thorough test mechanism to ensure the functionality and robustness of the circuit. This thesis employs the theory of relative timing that has the advantage of enabling designers to create designs that have significant power and performance over traditional clocked designs. Research has been carried out to enable the relative timing approach to be supported by commercial EDA tools. This allows asynchronous and sequential designs to be designed using commercial cad tools. However, two very significant holes in the flow exist: the lack of support for timing verification and manufacturing test. Relative timing utilizes circuit delay to enforce and measure event sequencing on circuit design. Asynchronous circuits can optimize power-performance product by adjusting the circuit timing.
A thorough analysis on the timing characteristic of each and every timing path is required to ensure the robustness and correctness of RT designs. All timing paths have to conform to the circuit timing constraints. This dissertation addresses back-end design robustness by validating full cyclical path timing verification with static timing analysis and implementing design for testability (DFT). Circuit reliability and correctness are necessary aspects for the technology to become commercially ready. In this study, scan-chain, a commercial DFT implementation, is applied to burst-mode RT designs. In addition, a novel testing approach is developed along with scan-chain to over achieve 90% fault coverage on two fault models: stuck-at fault model and delay fault model. This work evaluates the cost of DFT and its coverage trade-off then determines the best implementation. Designs such as a 64-point FFT, an I2C, a mixed-signal design are built to demonstrate power, area, performance advantages of the relative timing methodology and are used as a platform for developing the backend robustness. Results are verified by performing postsilicon timing validation and test. This work strengthens overall relative timed circuit flow, reliability, and testability

Thursday December 10, 2015
10:30 AM
Merrill Engineering Building (MEB) ECE conference room 2109
The public is invited

Farhana Masid-PhD final defense 12/9

UNIVERSITY OF UTAH
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT

DISSERTATION DEFENSE FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

by

Farhana Masid
Advisor: Rajesh Menon

Optical Patterning of Features in Sub-wavelength Size using Absorbance Modulation

Absorbance Modulation Optical Lithography (AMOL) is a new technique that promises to overcome the far field diffraction limit of conventional optical nano-patterning. An AMOL sample consists of a thin layer of photochromic molecules, which is referred to as the absorbance modulation layer (AML), on top of a conventional pattern recording medium, such as, photoresist. The photochromic layer has the property to transition between a transparent state when illuminated with ultra violet light (of wavelength λ1) and an opaque state when illuminated with visible light (of wavelength λ2). The sample is illuminated using a focused bright spot of wavelength λ1 (writing beam) and a focused ring-shaped spot of wavelength λ2 (confining beam). This simultaneous illumination of the sample ensures the formation of a sub-wavelength transparent region in the vicinity of the node of λ2, through which photons of λ1 penetrate and expose the underlying photoresist. Additionally, the pattern size does not depend on the absolute intensity of the exposing wavelength (writing beam), but on the ratio of the intensities of the two wavelengths.

In this thesis, a new process for AMOL that can overcome the limitations of the existing AMOL technique is demonstrated. This alternative method unlike the conventional method avoids removal of the AML and incorporates a favorable environment for photoresist development. This process has the added advantage of reusing the same AML for multiple disparate exposures. In the new technique, the arrangements of the layers of the sample are inverted. A quartz slide which is transparent to both wavelengths of interest is used as the main substrate and photoresist is used as the top and final layer. The illumination is carried out from the bottom of the sample, thereby allowing the development of the resist after exposure without removing the AML. Utilizing this new AMOL approach, with a writing wavelength of 325 nm and a confining wavelength of 647 nm, patterning of features with sizes of 60 nm (which is approximately equal to λ1 / 5.4) has been achieved. Moreover, spaces between resist features, as small as 119 nm has been successfully illustrated by moving the optical pattern relative to the sample. In addition, this thesis also discusses about a barrier free AMOL and a reverse AMOL technique and their advantages.


Wednesday December 9, 2015
9:00 AM
Merrill Engineering Building (MEB) ECE conference room 2109
The public is invited

Zhen Zhang PhD final thesis defense

UNIVERSITY OF UTAH
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT

DISSERTATION DEFENSE FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
by

Zhen Zhang
Advisor: Chris Myers

VERIFICATION METHODOLOGIES FOR FAULT-TOLERANT NETWORK-ON-CHIP SYSTEMS

Over the last decade, cyber-physical systems (CPSs) have seen significant applications in many safety-critical areas, such as automatic pilot avionics, autonomous automotive systems, wireless sensor networks, etc. A CPS uses networked embedded computers to monitor and control physical processes. The motivating example for this dissertation is the use of fault-tolerant routing protocol for a Network-on-Chip (NoC) architecture that connects electronic control units (ECUs) to regulate sensors and actuators in a vehicle. With a network allowing ECUs to communicate with each other, it is possible for them to share processing power to improve performance. In addition, networked ECUs enable flexible mapping to physical processes (e.g. sensors, actuators), which increases resilience to ECU failures by reassigning physical processes to spare ECUs. For the on-chip routing protocol, the ability to tolerate network faults is important for hardware reconfiguration to maintain the normal operation of a system. Adding a fault-tolerance feature in a routing protocol, however, increases its design complexity, making it prone to many functional problems. Formal verification techniques are therefore needed to verify its correctness. This dissertation proposes a link-fault tolerant, multiflit wormhole routing algorithm, and its formal modeling and verification using two different methodologies.

Improved upon the Glass and Ni’s routing algorithm that assumes node faults, this dissertation proposes a routing architecture extending that introduced by Wu et al. to a multiflit wormhole setting. It loosens Glass and Ni’s impractical assumption to achieve link-fault tolerance, covering a wider range of link fault cases that it fails to handle. Deadlock avoidance is implemented conservatively with adequate packet drops to break the cycle of dependencies. Simulation results indicate that this algorithm provides significant improvements in network reliability with minimal cost.

This link-fault routing algorithm is modeled in the process-algebraic language LNT. With the help of the CADP verification tool box, formal analysis exposes design flaws leading to false behaviors such as a packet leakage path leading to unintended packet drop and deadlock caused by removing arbiter’s buffering capacity. To combat the notorious state explosion problem, a data abstraction technique is applied to map the destination coordinates of a packet to a Boolean value representing its diversion status. Mismatch between the abstract and concrete models leads to the discovery of a potential livelock problem due to redundant packet diversions. Elimination of these diversions leads to an improved algorithm that simplifies the routing architecture, enabling successful compositional verification. The routing algorithm is proven to have several desirable properties including deadlock and livelock freedom, and tolerance to a single-link-fault.

As a comparison, the derived livelock-free routing protocol is modeled using the channel- level VHDL that is automatically compiled to labeled Petri-nets (LPNs) for verification using the LEMA tool.
Algorithms are described for an ample set based partial order reduction (POR) technique, which analyzes transition dependencies through a recursive trace-back search on LPNs. A set with the least number of enabled transitions that need interleaving is selected at each state. Cost and benefit of using trace-back are evaluated on several non-trivial asynchronous circuit models, and are compared to LNT models on a series of buffers that uses asynchronous communication. Finally, verification results are reported on using POR with trace-back on the livelock-free two-by-two NoC model.

Monday October 26, 2015
9:00 AM
ECE conference room, Merrill Engineering Building (MEB) Room 3235
The public is invited