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March 5th, 2012
Graduate Seminar
"A New Circuit Design Paradigm Exploiting Nonlinear Phenomena "
Wooram Lee
Ph.D. Candidate
Electrical and Computer Engineering
Cornell University
When: Monday, March 5th, 2012 at 3:05 p.m.
Where: Warnock 2250
Abstract
As Moore's law predicts, transistor scaling has continued unabated for more than half a century, resulting in significant improvement in speed, efficiency, and level of integration. This has led to rapid growth of diverse computing and communications technologies, including the Internet and mobile telephony. However, we still face the fundamental limit of noise from transistors and passive components, which determines the minimum sensitivity level in any system. This noise limit becomes more critical at higher frequencies due to the decrease in intrinsic transistor gain as well as with voltage scaling that accompanies the transistor scaling. On the other hand, insufficient transistor gain and breakdown in silicon limits high-power signal generation at sub-millimeter frequencies that is essential in many security and medical applications, including detection of concealed weapons and bio/molecular spectroscopy for drug detection and breath analysis for disease diagnosis.
To go beyond these limits, we have proposed a new circuit design methodology inspired by nonlinear wave propagation. This method is closely related to intriguing phenomena in other disciplines of physics such as nonlinear wave propagation in optics, fluid mechanics, and plasma physics. Based on this, in the first part of this presentation, we will propose a passive 20-GHz frequency divider for the first time implemented in CMOS. This device has close to ideal noise performance with no DC power consumption, which can potentially reduce overall system power and phase noise in high-frequency synthesizers. Next, to achieve sensitivity toward the thermal noise limit, this presentation will describe a 10-GHz CMOS noise-squeezing amplifier. This amplifier enhances sensitivity of an input signal in one quadrature phase by 2.5 dB at the expense of degrading the other quadrature component. Lastly, this talk will introduce an LC lattice to generate 2.7 Vp-p, 6 ps pulses in CMOS using constructive nonlinear wave interaction. The proposed lattice exhibits the sharpest pulse width achieved for high-amplitude pulses (>1 V) in any CMOS processes.
Speaker Biography
Wooram Lee (Ph.D.) received his B.Sc. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2001 and 2003, respectively, and is currently working towards his Ph.D degree at Cornell University, Ithaca, NY. He has held a summer internship at the IBM T.J. Watson Research Center in Yorktown Heights, NY, in 2011, where he worked on a millimeter-wave frequency multiplier in a 90-nm SiGe process. Before joining Cornell, he was a research engineer at the Electronics and Telecommunications Research Institute (ETRI), Daejeon, Korea, where he worked on optical transceivers and links from 2003 to 2007. His research interests include high performance RF IC design, exploiting nonlinear effects for signal generation and processing in very high frequency and low noise applications.
Mr. Lee received the IEEE Solid-State Circuits Predoctoral Fellowship for 2010-2011 and the Samsung Graduate Fellowship for 2007-2012. He was also a recipient of the Best Paper Award of the IEEE Radar Conference in 2009 and the IEEE workshop on Passive Microwave Circuits in 2010, and the Silver Medal at the National Physics Competition in 1996.