Phone:	(801) 587-7617
Fax:	(801) 581-5281
Office:	MEB 3254
E-mail:	kalla@ece.utah.edu
Web:	/~kalla

• Ph.D.,University of Massachusetts, 2002
• M.S., University of Masschusetts at Amherst, 1998
• B.E., Birla Vishvakarma Mahavidyalaya, 1993

• Logic validation and verification of high-level design descriptions.
• Logic synthesis and optimization for digital designs.
• Synthesis techniques for non-conventional design styles.
• System test and validation.
• Fundamental CAD techniques and algorithms.

Selected Publications

• BDD-based Logic Synthesis for LUT-based FPGAs. Navin Vemuri, Priyank Kalla and Russell Tessier. To appear in ACM Transactions on Design Automation of Electronic Systems (TODAES), Oct 2002.
• A Comprehensive Approach to the Partial Scan Problem using Implicit State Enumeration. Priyank Kalla and Maciej Ciesielski. IEEE Transaction on CAD, July 2002.
• Taylor Expansion Diagrams: A Compact Canonical Representation with Applications to Symbolic Verification. Maciej Ciesielski, Priyank Kalla and Bruno Rouzeyere. Design Automation and Test in Europe Conference, DATE, March 2002.
• Strategies for Solving the Boolean Satisfiability Problem using Binary Decision Diagrams. Priyank Kalla, Zhihong Zeng and Maciej Ciesielski. Journal of Systems Architecture, The Euromicro Journal. Sept. 2001.