`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:06:19 03/03/2009
// Design Name:   demo1
// Module Name:   C:/Documents and Settings/Administrator/demo1/TEST2demo1.v
// Project Name:  demo1
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: demo1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TEST2demo1;

	// Inputs
	reg [3:0] A;
	reg [3:0] B;

	// Outputs
	wire [4:0] C;

	integer i, j;
	
	// Instantiate the Unit Under Test (UUT)
	// In my case it is a 4-bit Adder C = A + B
	demo1 uut (
		.A(A), 
		.B(B), 
		.C(C)
	);

	initial begin
		// Initialize Inputs
		$monitor("Monitoring at time=%d: A = %d, B=%d, C= %d", $time, A, B, C);
		A = 0;
		B = 0;

		// Wait 100 ns for global reset to finish
		#100
			
			for(i=0; i<=15; i = i+1)
			begin
				for(j = 0; j<= 15; j = j+1)
				begin
				A = i;#1;
				B = j; #19;
				$display("------------------------------------");
				end
			end
		// Add stimulus here

	end
      
endmodule