Spring 2021, Final Exam Syllabus + Study aid 1. The whole of chapter 2: Boolean Logic, AND/OR, NAND/NOR circuits as universal logic, MUX based design, K-map, primes implicants, essentials, SOP minimization. 2. All of Chapter 3 except Section 3.7. Adders, multipliers and 2's complement concepts. 3. Everything in Chapter 4: MUXes, Decoders, Encoders, code-converters, Comparators. Also, Shannon's expansion of Boolean functions, implementation on MUXes. All these concepts combined with bit-vector arithmetic and 2's complement reasoning [Practise tests & mid-terms I & II] 4. All of chapter 5, except J-K Flip-flops. Level sensitive latches, edge-triggered DFFs, counters (synchronous and asynchronous), using DFFs and TFFs, shift registers, and Setup-Hold times + clock-period timing issues, effects of clock skew. 5. Chapter 6: Mealy and Moore machines, FSM design, State minimization, State encoding (also called state assignment), and synthesizing circuits using don't care conditions. 6. You may ignore chapter 7 for questions on the test. 7. Chapter 8: Functional decomposition: First go through my notes on the class website (last lecture) on simple disjunctive decomposition. You may ignore the generalization of simple decomposition to Ashenhurst-Curtis method. Then read section 8.1. For the Quine-McCluskey's table covering method, read Sec 8.4.1, and solve the related HW problems. 8. Implementation technology: You need to know basic concepts of PLAs (they implement 2-level logic), FPGAs (Look-up-table architectures) and Static CMOS gate design using pMOS (pull-up network) and nMOS (pull-down network). This is given in appendix B: upto Section B.7.