module mux4to1(W, C, f);
input [3:0] W;
input [1:0] C;
output f;
reg f;

// good way to design a MUX
always @(W or C)
begin
	if(C == 2'b00) f = W[0];
	else if(C == 2'b01) f = W[1];
	else if(C == 2'b10) f = W[2];
	else if(C == 2'b11) f = W[3];
	// all four cases considered

end

// this may work, but a bad idea!
/*---
always @(W or C)
begin
	f = W[2];
	if(C == 2'b00) f = W[0];
	else if(C == 2'b01) f = W[1];
	//else if(C == 2'b10) f = W[2];
	else if(C == 2'b11) f = W[3];

end
---*/

endmodule