Tenatative Schedule, we may make a few adjustments here and there, but
this is a nice way to go. I will adjust the schedule as the course progresses.
<p>
<li> Jan 10: Intro to the course. Logic Functions, Truth Tables, Boolean Algebra
<li> Jan 12: Boolean Algebra, DeMorgan's laws
<li> Jan 17: Synthesis and Implementation of Boolean Functions
<li> Jan 19: Transistors, CMOS logic, FPGAs + Synthesis, Verilog Intro
<li> Jan 24: Verilog design styles, simulation and synthesis
<li> Jan 26: Review of whatever we studied so far.... putting it all
  in perspective.  
<li> Jan 31:  Boolean Optimization, Algebra + K-Maps 
<li> Feb 2:  K-Maps, and Don't Care conditions
<li> Feb 7: Finishing Ch 2: Multi-level logic + CAD 
<li> Feb 9:  Number Representation, Adders, 
<li> Feb 14: Signed numbers + Two's   complement adders 
<li> Feb 16: Fast adders and array multipliers
<li> Feb 21: More 2's complement, Carry versus overflow, and Fast adders
<li> Feb 23: Chapter 4: Combinational Logic and Building Blocks
<li> Feb 28: Mux, decoders, comparators, etc.
<p>
<li>Mid Term I, March 3
<p>
<li> Mar 14: Behavioural Verilog
<li> Mar 16: Chapter 4 completion, Sequential Ckt. Intro to Latches, DFFs and Verilog.
<li> Mar 21 : Seq Ckts contd. (FFs, memory, regfiles)
<li> Mar 23: Verilog for registers and memories, counters
<li> Mar 28: Combinational + Sequential design concepts (counters)  
<li> Mar 30: Timing issues in sequential circuit design, clocking, skew
<li> Apr 4: Timing issues  and Ch 5 conclusion. Begin Finite State Machines (FSM) 
<li> Apr 6: Finite state machines (FSM)
<p>
<li> Tentatively Mid-Term 2 on April 7-10, [up to Chapter 5]
<p>
<li> April 11: FSM Optimizations 
<li> Apr 13:  FSM Optimizations + Analysis 
<li> Apr 18:  FSM Applications -- CPU design
<li> Apr 20: Advanced Digital Design Concepts - CAD Techniques
<li> Apr 25: CAD Techniques, Testing and Formal Verification