Tenatative Schedule, we may make a few adjustments here and there, but
this is a nice way to go....
<p>
<li>T, Jan 13: Intro to Logic Functions, Truth Tables, Boolean Algebra
<li>H, Jan 15: Boolean Algebra, 
<li>T, Jan 20: Transistors, CMOS logic
<li>H, Jan 22: FPGAs + Synthesis, Verilog Intro
<li>T, Jan 27: Boolean Optimization, Algebra + K-Maps
<li>H, Jan 29: K-Maps, Q-M method
<li>T, Feb 3: Q-M method contd....
<li>H, Feb 5:  Multi-level logic + CAD 
<li>T, Feb 10: Number Representation
<li>H, Feb 12:  Adders
<li>T, Feb 17: Signed numbers + Two's complement adders
<p>
<li>H, Feb 19: Mid-term I 
<p>
<li>T, Feb 24: Adders Contd., Intro to Multipliers 
<li>H, Feb 26: Multipliers, ASCII, BCD
<li>T, Mar 3 : Decoders + Demuxes 
<li>H, Mar 5: Combinational logic conclusions... 
<li>T, Mar 10 : Sequential Ckt. Intro 
<li>H, Mar 12: Seq Ckts contd. (FFs, memory, regfiles)
<li>T, Mar 24: Combinational + Sequential design concepts (counters) 
<p>
<li>H, Mar 26: Mid-Term II 
<p>
<li>T, Mar 31: Finite State Machines (FSM) 
<li>H  Apr 2: FSM Optimizations 
<li>T, Apr 7:  FSM Optimizations + Analysis 
<li>H, Apr 9:  FSM Applications 
<li>T, Apr 14: Advanced Digital Design Concepts - study of CPU design
<li>H, Apr 16: CPU Design Continued
<li>T, Apr 21: Asynchronous Circuits
<li>H, Apr 23: Asynchronous Circuits Contd....
<li>T, Apr 28: CAD Aspects of Digital Design: Synthesis, Test, Verification.