`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 11:47:36 01/29/2013 // Design Name: mux // Module Name: C:/Documents and Settings/Administrator/decoder/testmux.v // Project Name: decoder // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: mux // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module testmux; // Inputs reg x1; reg x2; reg x3; // Outputs wire f; //for simulation integer i, j, k; // Instantiate the Unit Under Test (UUT) mux uut ( .x1(x1), .x2(x2), .x3(x3), .f(f) ); initial begin // Initialize Inputs x1 = 0; x2 = 0; x3 = 0; // Wait 1 ns for global reset to finish #1; for(i = 0; i<2; i = i+1) begin for(j = 0; j < 2; j = j+1) begin for(k =0; k< 2; k = k + 1) begin x1 = i; x2 = j; x3 = k; #1; end end end // Add stimulus here end endmodule