`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Institution:	 University Of Utah
// Created by:		 Paymon Saebi 
// Create Date:    11/05/2013  
// Project Name: 	 CS/ECE 3710 - simple VGA template for Nexys 3
//////////////////////////////////////////////////////////////////////////////////

module VGA_Controller(input 				clock, clear,
							 output reg 		hSync, vSync, bright,
							 output reg [9:0] hCount, vCount);
	 
	 // ***********************************************************
	 initial   hSync  = 1; // Active low signal for the VGA port
	 initial   vSync  = 1; // Active low signal for the VGA port
	 initial   bright = 0; // Active high signal for the Bitgen circuit
	 initial   hCount = 0; // Horizontal pixel counter for the Bitgen circuit 
	 initial   vCount = 0; // Vertical pixel cunter for the Bitgen circuit
	 
 	 reg 	     clkDivPulse  = 0; // Used to notify every 25MHz clock tick
	 reg 		  hCountEnable = 0; // Used to enbales the horizontal pixel counter
	 reg 		  vCountEnable = 0; // Used to enbales the vertical pixel counter	
  	 reg [1:0] clkDivCount  = 0; // Used to count to 4 to determine the 25MHz ticks
	 reg [9:0] hTickCounter = 0; // Used to store the horizontal clock tick count
	 reg [9:0] vLineCounter = 0; // Used to store the vertical clock tick count	 

 	 // ***********************************************************
	 // Clock division pulse generator block

	 /* 
	  * Create a sequential block that generates an "enable" pulse for
	  * every 4 ticks of the 100MHz input clock
	  */
	
	 // ***********************************************************
	 // Horizontal and verical clock tick counters

	 /* 
	  * For the ease of generating the hSync and Vsync signals
	  * create two counters that count up to 800 for horizontal tick
	  * and (one line) and 581 for verital ticks every time you finish 
	  * a line. 
	  *
	  * Please note that this block should receive the same 100MHz clock
	  * and use the pulse generated above to enable the counting
	  *
	  * Please note that these cunters are different than then hCount
	  * and vCount counters as these only count up to 640 and 480 respectively
	  */
	 
	 // ***********************************************************
	 // Horizontal and vertical pixel counters
	 
	 /* 
	  * Same as above tick counters, these counters need to count up to
	  * 800 and 581 respectively, you can use the hCountEnable and
	  * vCountEnbale generated from the block below to enable their counting
	  *
	  * Please note that this block should receive the same 100MHz clock
	  * and use the pulse generated above to enable the counting
	  */
	  
	 // ***************************************************************
	 // Generate the hSync, vSync and bright signals
	 
	 /* 
	  * Based on the current counts on the hTickCounter and vTickCounter
	  * you can set the hSync, vSync and bright signal. Note that this 
	  * block is combinational, looks at the state of the counters and 
	  * reacts on the them to generate the outputs rigth away.
	  *
	  * Since the hCount and Vcount (640, 480) need to be determined 
	  * the same way using the above counters, it is helpful if you create 
	  * enable signals to help set them in their block above.
	  */
	  
	 // ***********************************************************
	 
endmodule

module VGA_Bitgen(input            bright, 
						input 	  [7:0] pixelData,
						input 	  [9:0] hCount, vCount,
						output reg [7:0] rgb);
	 
	 // ***********************************************************
	 parameter black   = 8'b000_000_00; // 8-bit black color
	 
	 // ***********************************************************
	 // Cobminational rgb setter
	 
	 /* 
	  * As described in the tutorial this circuit is a simple combinational
	  * block that sets the 8-bit rgb based on some pixel data.
	  */
	  
	 // ***************************************************************
	 
endmodule