`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:28:16 10/02/2013 
// Design Name: 
// Module Name:    memory 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
// This is a template for a single-port memory. 
// You should modify this to design a dual-port memory
//////////////////////////////////////////////////////////////////////////////////
	
	module memory( clk, en, we, din, addr, dout
    );
		parameter RAM_WIDTH = 16; //<ram_width>;
		parameter RAM_ADDR_BITS = 10; //<ram_addr_bits>;
		
 
	// Notice that the address bits = 10 implies 1024 words, which can be included in
	// one block. If this is increased to 11, the tool will map it to 2 BRAMs. 
	// View Tech Schematic.
	// RAM_ADDR_BITS = 15 will address 32 blocks of RAM. If this is extended to 16, then
	// the tool will also start synthesizing distributed RAM, and that will just be infeasible.
	
	 // Port A
	 input clk, en, we;
	 input [RAM_WIDTH-1:0] din;
	 input [RAM_ADDR_BITS-1:0] addr;
	 output reg [RAM_WIDTH-1:0] dout;
	 
	 // Port B description is your job
	 

   
   reg [RAM_WIDTH-1:0] the_memory_core [(2**RAM_ADDR_BITS)-1:0];
//   reg [RAM_WIDTH-1:0] <output_data>;
//
//   <reg_or_wire> [RAM_ADDR_BITS-1:0] <address>;
//   <reg_or_wire> [RAM_WIDTH-1:0] <input_data>;

   //  The following code is only necessary if you wish to initialize the RAM 
   //  contents via an external file (use $readmemb for binary data)
//   initial
//      $readmemh("<data_file_name>", <rom_name>, <begin_address>, <end_address>);

   always @(posedge clk)
      if (en == 1'b1) begin
         if (we == 1'b1) begin
            the_memory_core[addr] <= din;
				// In write-first mode, the din is also passed on to dout
            dout <= din;
         end
         else
            dout <= the_memory_core[addr];
      end
						

endmodule