[101]lab1-31:DEMO>> 
[101]lab1-31:DEMO>> sis
UC Berkeley, SIS 1.3 (compiled 2004-04-04 18:58:04)
sis> read_kiss fsm.kiss
//Run stamina, state_minimize invokes stamina
sis> state_minimize
Running stamina, written by June Rho, University of Colorado at Boulder
Number of states in original machine : 10
Number of states in minimized machine : 7
sis> 
//Run NOVA; state_assign by default will invoke either NOVA or JEDI if it finds
//them in the directory.
// So you could just run state_assign, which runs a greedy algorithm
// I invoked an input/output constrained assignment, it gives a
// different code than the greedy one, try both yourself
// Nova can also be invoked stand alone, type nova -h outside of SIS
sis> state_assign nova -e ioh
Running nova, written by Tiziano Villa,  UC Berkeley
Warning: network `SISEAAa02427', node "v0" does not fanout
Warning: network `SISEAAa02427', node "v1" does not fanout
Warning: network `SISEAAa02427', node "v2" does not fanout
Warning: network `SISEAAa02427', node "v3" does not fanout
// Now you can write the BLIF and see the code
sis> write_blif
.model fsm.kiss
.inputs IN_0 IN_1 IN_2 IN_3
.outputs OUT_0 OUT_1
.latch    v7.0 LatchOut_v4   0
.latch    v7.1 LatchOut_v5   0
.latch    v7.2 LatchOut_v6   0
.start_kiss
.i 4
.o 2
.p 42
.s 7
.r S0
--00 S0 S0 00
--01 S0 S0 00
--10 S0 S0 00
0011 S0 S0 00
1011 S0 S2 00
-111 S0 S1 00
--01 S2 S2 00
--10 S2 S2 00
--00 S2 S2 00
0011 S2 S0 00
-111 S2 S1 00
1011 S2 S4 00
--01 S1 S1 00
--10 S1 S1 00
--00 S1 S1 00
0011 S1 S0 00
-111 S1 S3 00
1011 S1 S2 00
--01 S4 S4 00
--10 S4 S4 00
--00 S4 S4 00
0011 S4 S2 00
-111 S4 S1 00
1011 S4 S6 00
--01 S3 S3 00
--10 S3 S3 00
--00 S3 S3 00
0011 S3 S1 00
-111 S3 S5 00
1011 S3 S2 00
--01 S5 S5 10
--10 S5 S5 10
--00 S5 S5 10
0011 S5 S0 00
-111 S5 S5 10
1011 S5 S2 00
--01 S6 S6 01
--10 S6 S6 01
--00 S6 S6 01
0011 S6 S0 00
-111 S6 S1 00
1011 S6 S6 01
.end_kiss
.latch_order LatchOut_v4 LatchOut_v5 LatchOut_v6
.code S0 000
.code S2 100
.code S1 010
.code S4 111
.code S3 001
.code S5 101
.code S6 110
.names IN_1 IN_2 IN_3 LatchOut_v4 LatchOut_v5 LatchOut_v6 OUT_0
1--101 1
-0-101 1
--0101 1
.names IN_0 IN_1 IN_2 IN_3 LatchOut_v4 LatchOut_v5 LatchOut_v6 OUT_1
--0-110 1
---0110 1
10--110 1
.names IN_0 IN_1 IN_2 IN_3 LatchOut_v4 LatchOut_v5 LatchOut_v6 v7.0
--0-1-- 1
---01-- 1
-0---11 1
1011--- 1
-111-01 1
.names IN_0 IN_1 IN_2 IN_3 LatchOut_v4 LatchOut_v5 LatchOut_v6 v7.1
--0--1- 1
---0-1- 1
-1--11- 1
1----11 1
10--110 1
-111-00 1
00110-1 1
1011100 1
.names IN_0 IN_1 IN_2 IN_3 LatchOut_v4 LatchOut_v5 LatchOut_v6 v7.2
--0---1 1
---0--1 1
-11101- 1
-111-01 1
1011100 1
.exdc 
.inputs IN_0 IN_1 IN_2 IN_3 LatchOut_v4 LatchOut_v5 LatchOut_v6
.outputs v7.0 v7.1 v7.2 OUT_0 OUT_1
.names LatchOut_v4 LatchOut_v5 LatchOut_v6 v7.0
011 1
.names LatchOut_v4 LatchOut_v5 LatchOut_v6 v7.1
011 1
.names LatchOut_v4 LatchOut_v5 LatchOut_v6 v7.2
011 1
.names LatchOut_v4 LatchOut_v5 LatchOut_v6 OUT_0
011 1
.names LatchOut_v4 LatchOut_v5 LatchOut_v6 OUT_1
011 1
.end
sis> 
sis> 
sis> 
sis> 
sis> print_stats
fsm.kiss      	pi= 4	po= 2	nodes=  5	latches= 3
lits(sop)=  95	#states(STG)=   7
sis> 
sis> 
sis> 
// Area-constrained logic optimization
sis> source script.rugged
sis> print_stats
fsm.kiss      	pi= 4	po= 2	nodes=  9	latches= 3
lits(sop)=  48	#states(STG)=   7
sis> 
sis> 
sis> 
// Read the library; -a appends a new library to an existing one
sis> read_library lib2.genlib
sis> read_library -a lib2_latch.genlib
// Tech mapping
sis> map
warning: unknown latch type at node '{v7.0}' (FALLING_EDGE assumed)
warning: unknown latch type at node '{v7.1}' (FALLING_EDGE assumed)
warning: unknown latch type at node '{v7.2}' (FALLING_EDGE assumed)
WARNING: uses as primary input drive the value (1.98,1.82)
WARNING: uses as primary input arrival the value (0.00,0.00)
WARNING: uses as primary input max load limit the value (999.00)
WARNING: uses as primary output required the value (0.00,0.00)
WARNING: uses as primary output load the value 0.10
sis> 
// Print delay (arrival times) of the top 10 latest arriving signals
sis> print_delay -a -p 10
 ... using library delay model
[511]     : arrival=(16.62 15.15) 
[750]     : arrival=(16.12 14.68) 
[527]     : arrival=(13.52 15.11) 
[688]     : arrival=(14.19 12.41) 
[496]     : arrival=(13.07 11.97) 
[512]     : arrival=(11.62 12.81) 
[751]     : arrival=(11.12 12.34) 
{OUT_1}   : arrival=( 9.78 11.62) 
[598]     : arrival=(10.55  8.92) 
[494]     : arrival=( 9.56  8.08) 
sis> 
// Lets see if this delay can be improved further
sis> source script.delay
WARNING: uses as primary input drive the value (1.98,1.82)
WARNING: uses as primary input arrival the value (0.00,0.00)
WARNING: uses as primary output required the value (0.00,0.00)
WARNING: uses as primary output load the value 0.10
WARNING: uses as primary output required the value (6.51,6.54)
WARNING: uses as primary output required the value (6.51,6.54)
# of outputs:          5
total gate area:       76096.00
maximum arrival time: (6.51,6.54)
maximum po slack:     (1.45,1.55)
minimum po slack:     (0.00,0.00)
total neg slack:      (0.00,0.00)
# of failing outputs:  0
sis> 
sis> print_delay -a -p 10
 ... using library delay model
[1528]    : arrival=( 6.51  6.54) /// Yes it can be
[1530]    : arrival=( 6.30  6.49) 
{OUT_1}   : arrival=( 5.96  6.42) 
[1529]    : arrival=( 6.35  6.40) 
[1948]    : arrival=( 6.01  6.07) 
[1984]    : arrival=( 5.80  6.01) 
[1947]    : arrival=( 5.85  5.93) 
[749]     : arrival=( 5.54  5.30) 
[1737]    : arrival=( 5.40  4.88) 
[1986]    : arrival=( 5.35  5.09) 
sis> 
// Sequential optimization
sis> retime 
Lower bound on the cycle time =  2.94
Retiming will minimize the cycle time 
RETIME: Initial clk = 8.93 , Desired clk = 2.94 
initial cycle delay         = 8.93 
initial number of registers = 3
initial logic cost          = 62176.00
initial register cost       = 13920.00

Failed at 2.94  : Now attempting 5.93 
Failed at 5.93  : Now attempting 7.43 
Failed at 7.43  : Now attempting 8.18 
Failed at 8.18  : Now attempting 8.55 
Success at 8.55 , Delay is 8.27 


final cycle delay         = 8.27 
final number of registers = 7
final logic cost          = 62176.00
final register cost       = 32480.00

RETIME: Final cycle time  achieved = 8.27 
sis> print_delay -a -p 10
 ... using library delay model
[2017]    : arrival=( 6.58  7.47) 
[2023]    : arrival=( 7.02  6.05) 
[1984]    : arrival=( 6.08  7.00) 
{OUT_1}   : arrival=( 6.11  6.97) 
[2029]    : arrival=( 5.81  6.60) 
[2032]    : arrival=( 6.53  5.55) 
[749]     : arrival=( 6.52  5.58) 
[1747]    : arrival=( 6.52  5.57) 
[1739]    : arrival=( 5.31  6.13) 
[1737]    : arrival=( 6.03  5.07) 

/// Retiming on its own may not be beneficial, but it enables
subsequent delay optimization
sis> source script.delay
WARNING: uses as primary input drive the value (1.98,1.82)
WARNING: uses as primary input arrival the value (0.00,0.00)
WARNING: uses as primary output required the value (0.00,0.00)
WARNING: uses as primary output load the value 0.10
WARNING: uses as primary output required the value (5.89,5.88)
WARNING: uses as primary output required the value (5.89,5.88)
# of outputs:          9
total gate area:       115072.00
maximum arrival time: (5.89,5.88)
maximum po slack:     (1.16,1.23)
minimum po slack:     (-0.00,0.00)
total neg slack:      (-0.00,0.00)
# of failing outputs:  1
sis> print_delay -a -p 10
 ... using library delay model
[2820]    : arrival=( 5.89  4.92) 
{OUT_1}   : arrival=( 5.35  5.88) 
[2824]    : arrival=( 5.82  5.82) 
[2821]    : arrival=( 5.79  5.66) 
[2822]    : arrival=( 5.71  5.74) 
[2825]    : arrival=( 5.73  5.74) 
[2823]    : arrival=( 5.67  5.05) 
{OUT_0}   : arrival=( 5.41  5.56) 
[3396]    : arrival=( 5.39  4.44) 
[3392]    : arrival=( 5.32  5.34) 
sis> 
sis> write_blif fsm.blif
sis> 
// This writes a MAPPED blif
sis> write_blif -n fsm.n.blif
sis> 
sis> quit
[102]lab1-31:DEMO>>