Spring 2018: Fundamentals of Digital System Design
ECE3700, CPSC 3700
Meets Tue, Th, 12:25pm to 1:45pm, WEB 1230.
Instructor
Priyank Kalla
Office: MEB 2260 (Near the ECE advising suite)
Tel: 587-7617, Email: kalla [at] ece.utah.edu
Office hours: Tuesdays 2-3pm; Wednesday 1 - 2pm, or by appointment.
Course Description
Textbook: Fundamentals of Digital Logic with Verilog
Design. Third Edition, c 2014.
Available at the bookstore (858 pgs ISBN: 9781307162318)
Authors: Brown and Vranesic. McGraw Hill Publishers.
This is a good book that contains all the topics that we need to cover
in the class - basics + mathematical
concepts + circuit design issues + CAD - everything that we will cover
in the class. The book is available in the bookstore.
From time to time, I will prepare some extra class notes and upload
them on the class-webpage for your reference.
Here is an informal
description of the course.
Here is the class schedule
that we will strive to adhere to. This can also act as your reference
regarding the course syllabus, material covered in class and the
corresponding chapters and sections in the textbook.
Grading Policy
Homework Assignments: 15%
Laboratory Assignments: 25%
Mid-Term Exam I: 15%
Mid-Term Exam II: 15%
Final Exam: 30%
Bureaucratic/Paperwork/Organizational Stuff
Teaching Assistants
There are 3 Lab TAs, and one HW grader
- Lab TA, Harikrishna Subramanyam : u1073799 [at] utah.edu: In
addition to Lab hours, he will hold office hours also in DSL (MEB
3133) right after his labs: Mon 3:30 - 4pm; Wed: 4:30 - 5pm; Fri:
10:30 - 11:30am.
- Lab TA, Utkarsh Gupta : utkarsh[dot]gupta [at]
utah.edu. Office hours will also be held in DSL MEB3133 right
BEFORE his lab: Thursday 2:30pm - 3:30pm.
- Lab TA, RajathSuparna Bindiganavile rajath[dot]bindiganavile [at]
utah.edu. Office hours will also be held in DSL MEB 3133 around his
lab hours: Tuesday 10 - 10:30am (before the lab), Wed 12-1pm (after
the lab), and Thu 10 - 10:30 (before the lab).
- HW TA and grader: Sayed Abdullah Sadat ,
s.sadat@utah.edu, Office hours: Thursday 3pm to 5pm, MEB 2231.
Canvas page for class, for Mailing Lists, Discussions and Submissions
I have created a Canvas Webpage for the course too. The URL is:
https://utah.instructure.com/courses/482796.
All the lecture materials will be delivered through
my
official UofU webpage at the CADE lab server . However, the Canvas
webpage is setup so you can use it for emailing me, or the TAs or
fellow students, use of the discussion board, submission of HW/Lab
reports, etc.
The reason I'm using my offical UofU webpage for class materials is
due the trmendously more flexibility it provides in providing you
with all the necessary materials, information, and resources for the
class.
Lab Sessions HAVE TO BE assigned based on yours and TAs availabilities
Lab sessions begin the second week of class, from Jan 15, 2018
onwards. .
Labs will start from the second week of class, i.e. from Jan 15
onwards. The first lab is an intro to the kit which will be
checked out to you, and a simple logic circuit design using the
kit. Labs will be held in MEB 3133, Junior Hardware Lab (formerly,
also known as the Digital Systems Lab (DSL)).
You will be provided "card access" to this lab.
Seven (7) Lab sessions have been created.
- Lab #1, Monday, 2:00pm - 3:30pm
- Lab #2: Tuesday, 10:30am - 12pm
- Lab #3: Wednesday, 10:30am - 12pm
- Lab #4: Wednesday, 3:00pm - 4:30pm
- Lab #5: Thursday, 10:30am - 12:00pm
- Lab #6: Thursday, 3:30pm - 5:00pm
- Lab #7: Friday, 9am - 10:30am
Please use this Doodle Poll to fill out your preferences for the lab sessions.
Over the weekend, we will email you your assigned lab session.
Course Downloadables
Lecture Notes and Slides
Lecture 1, Jan 9: Introduction to the course. We introduce basic
logic functions: AND, OR, NOT, XOR, and truth tables.
Lectures 1-2, Jan 9-11: We will continue our study of algebraic
operations on Boolean functions, De Morgan's laws, and solve a design
problem. Most of this is given in Chapter 2, so here are some slides
for your reference:
Lecture 3, Jan 16: We'll continue our discussions on logic design
and simplifcation, solve some digital circuit design and optimization
problems with 3- and 4-input Boolean functions, and study the
remaining basic concepts related to Ch 2.
- We will be ready to start thinking of implementing Boolean
functions using TTL ICs and FPGAs. Here are
some slides from Appendix B.
Lecture 4, Jan 18: Synthesis and Implementation of Boolean Functions
- 2-level logic, SOP forms and POS forms (Sec 2.6)
- Universal Logic, AND/OR/NOT, NANDs only, NORs only (Sec 2.7)
- Implementation on PLAs (Appexdix B, B.6.1, B.6.2)
- Factored forms and CMOS logic (Appexdix B, Section B.3)
- Multiplexor functions and FPGAs (Appendix B, Section B.6.5)
Lecture 5, Jan 23: CMOS gates, factored forms, MUX based design
and FPGAs. Time permitting, an introduction to Verilog
Lecture 6, Jan 25: An introduction to Verilog HDL.
- Here are the mux.v
and testmux.v verilog files that
we saw in class on 1/25. The file testmux.v is the testbench,
take a look at the organization of signal assignments and signal
declarations.
Lecture 7, Jan 30: The study of K-maps for SOP
minimization. Will also study incompletely specified Boolean
functions, i.e. functions with don't care conditions and how they
are used in optimization. For K-maps, we'll make use of the
following terminology: minterms, cubes, implicants, prime
implicants.
Lecture 8, Feb 1: This will complete Chapter 2, and we will begin
Chapter 3 in earnest: Arithmetic computations and computations on
Vectors of Bits. Here are the chapter 3 slides:
Lecture 9, Feb 6: Will study Arithmetic. Introduced integer
encoding of bit-vectors. Design of Half adders and Full
adders. Cascading of 1-bit full adders to build n-bit ripple-carry
adders. Also start discussing signed numbers and subtraction with 1s and 2s complement schemes.
Lecture 10, Feb 8: 2's complement arithmetic and the concept of overflow.
Lecture 11, Feb 13: Review of 2's Complement arithmetic, carry
versus overflow, design of a combined adder/subtractor unit, and
Verilog's interpretation of signed and unsigned numbers (bit vectors!)
Lecture 12, Feb 15: Carry Lookahead adders and unsigned array
multipliers design.
Lecture 13, Feb 20: Chapter 4: And now we will move on to the
next set of topics, is about combinational logic building blocks,
and how they can be put together to build larger systems. We will
study the design of comparators, multiplexors and decoders.
Lecture 14, Feb 22: Design examples with a combination of adders,
MUXes, decoders and Comparators. Also, verilog design using always blocks.
Lecture 15, Feb 27: Decoders and behavioural Verilog, Case
statements, decoder based designs.
Lecture 16, March 1: Mid Term Exam I.
Lecture 17, March 6: Complete Ch 4 by studying various code
converters, the BCD to 7-segment display decoder, their design using
CASEX statements, and move on to memories.
Lecture 18, March 8: Study of Memories, cross-soupled NAND and
NOR gate based SR latch, and gated D-latches.
Lecture 19, March 13: Level-sensitive Latch versus edge-triggered
memories, Edge triggered DFFs, Master-slave design.
Lecture 20, March 15: Blocking and Non-blocking assignments in
Verilog, the issue of synchronous updates of DFFs, counter design in
Verilog.
March 18-25 Spring break, YAY!
Lecture 21, March 27: Reset issues in DFFs, Verilog design of
counters with reset and pause signals, TFFs, asynchronous counters
with TFFs, shift registers.
Lecture 22, March 29: Complete the discussion on counters. Study
timing issues in sequential circuit design. Then move on to general
purpose finite state machines.
Please study timing issues given in Section 5.15.
Lecture 23, April 3: The notion of state equivalence and
distinguishability, and their application to state
minimization. Here are some
more slides with example FSMs that we will solve in class
today.
Lecture 24, April 5: We studied examples of FSM design for both
Mealy and Moore type, and learned how to synthesize a FSM from it's
state transition graph: State Encoding + generating next-state and
output logic for the sequential circuit.
Lecture 25: April 10, Mid term II.
Lecture 26: April 12, We studied concepts of FSM minimization of
Mealy and Moore Machines. Here
are the examples FSMs that we minimized in class. Also given in
Sections 6.1 and 6.2 in the textbook.
Lecture 27, April 17: Today, we will study the concepts on how to
describe Moore and Mealy FSMs as Verilog Code. Given in Section 6.4
in the textbook. After that we will move on to chapter 8, and study
two advanced concepts: i) Logic minimization of SOP forms using the
Quine-McCluskey's method; and ii) How to perform functional
decomposition. Here are the slides from chapter 8:
Lecture 28, April 19: Quine-McClusky's method of Table covering
to solve the two-level SOP form minimization problem.
Lecure 29, April 24: Functional Decomposition and course
review. Here are the notes that I used in
class: Boolean function
decomposition: simple disjunctive decomposition, and it's
generalization Ashenhurst-Curtis decomposition.
Homework and Reading Assignments
Reading Assignment, the week of 01/9 - 01/15: Chapter 1.
Reading Assignment, the week of 01/22-01/29: Chapter 2, up to
Section 2.8. Appendix B, Sec B.1, B.3, B.5, B.6.
HW 1 is assigned, download it from
here. Due Tuesday, Jan 30, please deposit a paper copy in the 3700 HW
locker #26, 2nd floor MEB. The lockers are near my office in the
hallway.
HW 1 due date extended to Tuesday Jan 30.
Reading Assignment, the week of 2/4-2/11, complete reading of Ch 2
in the textbook. Also read Appendix B, Sections B.6 and B.7.
HW 2 is assigned, download it from
here. Due Feb 13, please drop it in the 3700 HW locker, 2nd floor
MEB, near ECE office.
Reading assignment for Arithmetic: Read the chapter upto (excluding)
Section 3.7; i.e. up to pp. 170.
HW 3 is assigned, download it from
here. Due Tuesday Feb 27, please drop it in the 3700 HW locker,
2nd floor MEB, no later than 5pm. At 5pm, I will upload the solutions.
Reading assignment for HW 4: Read Ch 4 completely, except you
may ignore Verilog Tasks and functions for now. In Chapter 5, read
upto Sec 5.9.
Reading assignment for HW 5: Read chapter 6, Sections 6.1, 6.2, 6.3, 6.5, 6.6.1, 6.6.2, ignoring other sections. Also read sections 8.3.1, and 8.4 to solve the last 2 questions on the HW.
Laboratory Assignments
Lab assignment 1
Download Lab assignment 1 from here
. The assignment is due by your lab sessions Jan 30 to Feb
5. Have your design and circuit checked off by your TA during the
labs and upload your lab report on Canvas by the due date.
You may also need to refer to the following documents:
Now that you are receiving the lab kits, here is a document
that introduces the contents of the kit to you . Note that this
document has a few guidelines/suggestions on how to use the components
in the kit.
Here is a reference for some
useful ICs in your kit . Note that you do not have ALL these ICs
in the kit, some of the memories and counter circuits will not be
used, so they have been removed from you kit.
Here are some datasheets for the 74XX series ICs listed as MM74HC**.pdf
.
While the above does not cover all the ICs in our kit, here is a site
with a more comprehensive set of datasheets. Datasheets
provide you information about pinouts, voltage and current limits,
timing and other information on how to use the chips.
Here is a link to the
Nexys 3 reference manual.
Here is a link to the Nexys 3 main page:
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3&CFID=302233&CFTOKEN=87818199
Here is a link VMOD-WW VHDC wire-wrap board.
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,648,848&Prod=VMOD-WW . Scroll
down to the bottom of the page and you can view/download schematics
and manuals for the board.
Lab assignment 2
Here is Lab assignment 2 . Due
the week of 2/13-2/19. In this lab, you will use the Xilinx ISE
Webpack Tools, installed on your lab machines, to design, simulate,
synthesize and download the design to the FPGAs. The tools can also
be downloaded on your personal computers for free. See the
instructions below.
Also linked below is a tutorial (UPDATED) prepared by
Prof. Brunvand and Paymon (my prior TA) and updated by Utkarsh that
describes the downloading and installation of the Xilinx ISE
software, along with an introduction to design, simulation and
synthesis of circuits. It will be very
helpful:
UPDATED tutorial on the use of Xilinx ISE 14.7.
Here are the mux.v
and testmux.v verilog files that
we saw in class on 1/25. The file testmux.v is the testbench,
take a look at the organization of signal assignments and signal
declarations.
Lab assignment 3
Here is Lab assignment 3 . Due
the week of 2/27-3/5. Design of ripple-carry and look-ahead adder circuits.
Lab assignment 4
Here is Lab assignment 4 .
Due by Monday 3/12. Design of unsigned and two's complement
comparators. Only Verilog design, simulation and synthesis. No need
to download to the FPGA. Note this is a short, 1-week lab.
Lab assignment 5
Here is Lab assignment 5 . Due
the week of 4/2-4/6. Design of a stop-watch timer.
Lab assignment 6
Here is Lab assignment 6. A
'restricted' CPU and control design; or a music/tone generator. Demo
due the week of 4/17-4/23; optional checkoff on reading day. Final
report due by 4/27.
For the music generator you will also need the Habanera composition and the audio MIDI file.
Musical note frequencies can be found at:
https://pages.mtu.edu/~suits/notefreqs.html .
Those of you who plan to design the music and tone generator, you
will have to make use of the PMOD that can be hooked up to the FPGA
board and the speaker should be connected to the PMOD to get proper
and louder sound. A tutorial instruction for that can be found at:
pmod_ref.pdf.