Spring 2015: Fundamentals of Digital System Design
ECE3700, CPSC 3700
Meets Tue, Th, 12:25pm to 1:45pm, WEB 1230.
Office: MEB 4512 (East side Penthouse on the fourth floor)
Tel: 587-7617, Email: kalla [at] ece.utah.edu
Office hours: Thursday 2:30pm - 4pm; or by appointment.
Textbook: Fundamentals of Digital Logic with Verilog
Design. Third Edition, c 2014.
Authors: Brown and Vranesic. McGraw Hill Publishers.
This is a good book that contains all the topics that we need to cover
in the class - basics + mathematical
concepts + circuit design issues + CAD - everything that we will cover
in the class. The book is available in the bookstore.
From time to time, I will prepare some extra class notes and upload
them on the class-webpage for your reference.
Here is an informal
description of the course.
Here is the class schedule
that we will strive to adhere to. This can also act as your reference
regarding the course syllabus, material covered in class and the
corresponding chapters and sections in the textbook.
Homework Assignments: 15%
Laboratory Assignments: 25%
Mid-Term Exam I: 15%
Mid-Term Exam II: 15%
Final Exam: 30%
Mid Term Exam I, scheduled for Tue Mar 3, in class
Will cover materials from chapters 1, 2 and 3 completely, and
only section 4.1 in chapter 4 (up to Multiplexors).
Please download the practise test from
Practise exam solutions are
Mid Term Exam II, scheduled for Thursday April 9, in class
Please download the practise test from
Syllabus: i) Full Chapter 4, ii) Full Chapter 5, iii) Addition
and subtraction (2's complement) from Ch 3; iv) Cannot ignore Boolean
Solutions to the practise test:
- For questions 1 & 2,
- the modulo-6 counter is given in the textbook, Fig. 5.26. The
main thing to see is how the counter is reset at count = 6. Of
course, this is an up counter, but you have designed a synchronous
down counter as in HW 4, Q6 already.
- Solution to problem 5.21 is already given in the textbook, on
- Solution to Q5 is
Final Exam on Friday May 1, 10:30-12:30pm
This is confirmed through the Univ. exam schedule, given
Exam is closed book, closed notes, and comprehensive.
Here is a detailed syllabus for the final exam:
Final exam syllabus
Here are some
practice questions for the final exam.
Solutions to some of the questions
can be downloaded from here .
There are 3 Lab TAs, and one HW grader + TA
- Lab TA, Sec 2, 8: Trevor Hill : u0628184 [at] utah.edu: In
addition to Lab hours, he will hold office hours also in DSL (MEB
3133). Hours: Monday and Wednesday: 10:30am - 11:30am.
- Lab TA, Sec 3, 6, 9: Utkarsh Gupta : utkarsh[dot]gupta [at]
utah.edu. Office hours will also be held in DSL MEB3133. Hours:
TUE: 5PM-5:30PM; WED: 2-3pm; and FRI: 12:55PM - 1:25PM.
- Lab TA, Sec 4, 5, 7: Steven Brown u0499404 [at]
utah.edu. Office hours: Wed 11-11:50am, Thu 5 - 5:30pm, Fri
2:30-3pm, will be held in DSL MEB 3133.
- HW TA and grader: Sanath Kondur Surya Kumar , u0873305 [at]
utah.edu. Office hours: Tue 4-5pm, Wed 12-1pm, Thu 4-5pm. Office
hours will be held in the TA lounge MEB 2340.
Class Mailing Lists
A class mailing list 'firstname.lastname@example.org' has been created to
communicate with the whole class. Of course, each student will have to
"subscribe" to this list to be able to send and receive messages.
To subscibe to this list, you should do the following:
You will be asked to confirm your subscription request before it
can be processed. Please conform to the instructions contained
in the message you receive.
You'll receive a welcome message, and that should be it.
- From your email account (the one that you use primarily), send an
email message to email@example.com
- The 'subject' of your message should be: subscribe
firstname.lastname@example.org Firstname Lastname
- Leave the message body blank.
Lab Sessions HAVE BEEN assigned
Lab sessions begin the second week of class, from Jan 20, 2015
onwards. Please go to your assigned
lab sessions to pick-up your lab kits .
Labs will start from the second week of class, i.e. from Jan 20
onwards. The first lab is an intro to the kit which will be
checked out to you, and a simple logic circuit design using the
kit. Labs will be held in MEB 3133, Junior Hardware Lab (formerly,
also known as the Digital Systems Lab (DSL)).
You will be provided "card access" to this lab.
A request to a few students enrolled in Lab section 4: Wed
11:50 - 1:10. This lab is at full capacity. If some of you
(around 4-5 students) are interested in and willing to transfer to
other lab sections, then the following sections have very low
If anyone is interested in moving, just send an email to the TAs,
and CC it to me. We can make these adjustments internally, and you
do not have to formally re-enroll in a different lab section.
- Lab section 5, Thursday 3:40-5pm
- Lab section 7, Friday 3-4:20pm
- Lab section 9, Wednesday 3-4:20pm
Lecture Notes and Slides
Lecture 1, Jan 13:
Introduction to the course. We also introduced basic logic
functions: AND, OR, NOT, XOR, and truth tables.
Lectures 1-2, Jan 13-15: We will continue our study of algebraic
operations on Boolean functions, De Morgan's laws, and solve a design
problem. Most of this is given in Chapter 2, so here are some slides
for your reference:
Lecture 3, Jan 20: We'll continue our discussions on logic design
and simplifcation, solve some digital circuit design and optimization
problems with 3- and 4-input Boolean functions. and study the
remaining basic concepts related to Ch 2:
Lecture 4, Jan 22: Study of universal Logic: MUX design, NAND/NOR
universal logic, Maxterms, etc.
Lecture 5, Jan 27: Introduction to Verilog, and study of K-maps
for Boolean function minimization into minimized SOP forms.
Lecture 6, Jan 29: The study of K-maps for SOP minimization. Will
also study incompletely specified Boolean functions, i.e. functions
with don't care conditions and how they are used in optimization.
This will complete Chapter 2, and we will begin Chapter 3 in
earnest: Arithmetic computations and computations on Vectors of
Bits. Here are the chapter 3 slides:
Lecture 7, Feb 3: K-maps with don't cares completed, and briefly covered
the architecture of Programmable logic arrays (PLAs) and Field
Programmable Gate Arrays (FPGAs), given in Appendix B.6, B.7.
Lecture 8, Feb 5: Will study Arithmetic. Introduced integer
encoding of bit-vectors. Design of Half adders and Full
adders. Cascading of 1-bit full adders to build n-bit ripple-carry
adders. Covered Sections 3.1.1, and 3.2.
Lecture 9, Feb 10: Verilog Design of ripple-carry adders. The
concept of component instantiation. Given in Sections 3.5.1 - 3.5.3,
pp. 151-155. Then, we will study the concept of signed arithmetic:
mainly the very important 2's complement arithmetic.
Lecture 10, Feb 12: 2's complement arithmetic, and its
relationship to modulo arithmetic. The concept of overflows and
carry-signals, and how they are different concepts. Design of logic
circuits for 2's complement addition and subtraction. This is given
in Section 3.3 and 3.4. Time permitting, we will study fast-adders.
Lecture 11, Feb 17: Review of 2's Complement arithmetic, carry
versus overflow, design of a combined adder/subtractor unit, and
Verilog's interpretation of signed and unsigned numbers (bit vectors!)
Lecture 12, Feb 19: And now we will move on to study of
fast-adders and multipliers. This will complete our study of Chapter
3. Next topic, from Chapter 4 is about combinational logic building
blocks, and how they can be put together to build larger systems.
Lecture 13, Feb 24: Multipliers and Chapter 4 (MUXes, decoders, etc.)
Lecture 14, Feb 26: Chapter 4, Shannon's expansion and MUX-based designs
Lecture 15, March 3: Mid-term test
Lecture 16, March 5: Decoders and behavioural Verilog.
Lecture 17, March 10: More Verilog, Case statements, decoder based
Lecture 18, March 12: Complete Ch 4 by studying the BCD to 7-segment
display decoder, their design using CASEX statements, and move on to
memories. Here are some examples we looked at in the
class: compare.v, decoder.v , mymux.v,
saturation_arith.v . Please
study these Verilog codes, synthesize them, try to indentify if the
code is correct or has a bug.
March 16-20 Spring break, YAY!
Lecture 19, March 24: Begin introduction to sequential circuits,
memory elements, latches versus edge-triggered flip-flops, an
introduction to counter design, and some new Verilog behavioural
Lecture 20, March 26: In the last lecture, I gave a black-box overview of
level sensitive latches and edge-triggered DFFs. Now, we will take
a detail look inside these black-boxes and learn how they are
designed, what timing issues do they have, and then proceed to
designing some real/meaningful circuits using these memory devices.
Lecture 21, March 31: Now that we know how latches and FFs are
designed, we will study how to design counters and shift
registers. We will also introduce the concept of non-blocking
assignments in Verilog to design circuits using edge triggered
Lecture 22, April 2: Timing issues in sequential circuits:
Setup-time, Hold-time, Propoagation delay (or clock-to-Q
TCQ time), and techniques to derive the operating
Lecture 23, April 7: Complete chapter 5, with design of counters
and shift registers. Then, motivate the concept of finite state
machines (FSMs) through Lab 6, and start designing & optimizing
Lecture 24, April 9: Mid-Term II
Lecture 25, April 14: Finite State Machines: Design, optimization
and synthesis. Here are Chapter 6 slides:
Lecture 26, April 16: The notion of state equivalence and
distinguishability, and their application to state
minimization. Here are some
more slides with example FSMs that we will solve in class
Lecture 27, April 21: Complete Ch 6 with more FSM design
examples, Verilog styles for FSM implementation, and overview of Ch
Here are Chapter 7 slides:
Lecture 28, April 23: Functional decomposition (Sec 8.1 + 8.2) +
CMOS gate design (Appendix B, B.3).
Lecure 29, April 28: Course review.
Homework and Reading Assignments
Reading Assignment, the week of 01/12 - 01/19: Chapter 1.
Reading Assignment, the week of 01/19-01/23: Chapter 2, up to
HW 1 is assigned, download it from
here. Due Jan 30, please drop it in the 3700 HW locker, 2nd floor
MEB, near ECE office.
Solutions to HW 1 can be downloaded from
Reading Assignment, the week of 2/2-2/6, complete reading of Ch 2
in the textbook. Also read Appendix B, Sections B.6 and B.7.
HW 2 is assigned, download it from
here. Due Feb 11, please drop it in the 3700 HW locker, 2nd floor
MEB, near ECE office.
HW 2 solutions can be obtained from
here. Solutions prepared by
HW 3 is assigned, download it from
here. Due Friday Feb 27, please drop it in the 3700 HW locker, 2nd floor
MEB, no later than 5pm. At 5pm, I will upload the solutions.
Reading assignment for HW 3: Read the chapter upto (excluding)
Section 3.7; i.e. up to pp. 170.
Solutions for HW 3 can be found over
here; solutions prepared
Reading assignment for HW 4: Reach Ch 4 completely, except you may ignore Verilog Tasks and functions for now. In Chapter 5, read upto Sec 5.9.
HW 4 is assigned. Download it from
HW 4 solutions are
Reading assignment for HW 5: Read chapter 6, Sections 6.1-6.9
(ignoring JK flip-flops).
HW 5 is assigned. Download it from
here. Due Wed 4/29, 5pm.
HW 5 solutions: Part 1
and Part 2 and for
washing machine FSM
Lab assignment 1
Download Lab assignment 1 from here
. You will also need to refer to the following documents:
Now that you are receiving the lab kits, here is a document
that introduces the contents of the kit to you . Note that this
document has a few guidelines/suggestions on how to use the components
in the kit.
Here is a reference for some
useful ICs in your kit . Note that you do not have ALL these ICs
in the kit, some of the memories and counter circuits will not be
used, so they have been removed from you kit.
Here are the datasheets for the 74XX series ICs listed as MM74HC**.pdf
Here is a link to the Nexys 3 reference manual:
Here is a link to the Nexys 3 main page:
Here is a link VMOD-WW VHDC wire-wrap board.
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,648,848&Prod=VMOD-WW . Scroll
down to the bottom of the page and you can view/download schematics
and manuals for the board.
Lab assignment 2
Here is Lab assignment 2 . Due
the week of 2/16-2/20. In this lab, you will use the Xilinx ISE
Webpack Tools, installed on your lab machines, to design,
simulate, synthesize and download the design to the FPGAs.
Here are the mux.v
and testmux.v verilog files that
we saw in class on 1/27. The file testmux.v is the testbench,
take a look at the organization of signal assignments and signal
Also linked below is a (UPDATED) tutorial prepared by Paymon (my prior TA) that will be very helpful:
The Xilinx ISE-WEBPACK FPGA Design and Synthesis Software is
available for free download for Windows and Linux platforms. Please
feel free to download and install the latest version of the software
Xilinx ISE Webpack site. It may require that you register to
create an account with them first. They have a version 14.7
available, whereas the tutorial above is for V. 14.4. However, the
front-end interface of the tools is pretty much the same, nd you
shouldn't have much of a problem.
Lab assignment 3
Here is Lab assignment 3 . Due
the week of 3/2-3/6. Design of ripple-carry and look-ahead adder circuits.
Lab assignment 4
Here is Lab assignment 4 .
Due by Friday 3/13. Design of unsigned and two's complement
comparators. It'll make you think of the design just a little bit!
Lab assignment 5
Here is Lab assignment 5 . Due
the week of 4/13-4/17. Design of a stop-watch timer.
Lab assignment 6
Here is Lab assignment 6. A
'restricted' CPU and control design; or a music/tone generator. Demo
due the week of 4/20-4/24; optional checkoff on reading day. Final
report due by 4/29.
For the music generator you will also need the Habanera composition and the audio MIDI file.
Musical note frequencies can be found at: