Digital VLSI Design
ECE/CS 5710/6710
Fall 2014

Online Required Textbook:

Crafting a Chip
A Practical Guide to the
UofU VLSI CAD Flow

by Erik Brunvand


This is the "lab book" for the class.

This is an online version of an pre-publication draft of the book that has been made available on-line from Dr. Brunvand.

Please respect the copyright and only use this book for the course. Do not distribute any section of this book or make it available on the web!

You will only be able to access this book from the University of Utah web site. If you are off-site you will need to log on using the Utah VPN Client on the web.

Note: The there is an update for the book to map from the version 5 to version 6 of the Cadence desing tool interfaces. You will need to use this in conjunction with the book to efficiently use the tools.


CONTENTS:
Title page and table of contents
Chapter 1: Getting Started
Chapter 2: Cadence Design Framework
Chapter 3: Composer Schematic Capture
Chapter 4: Verilog Simulation
Chapter 5: Virtuoso Layout Editor
Chapter 6: Spectre Analog Simulation
Chapter 7: Cell Characterization
Chapter 8: Verilog Synthesis
Chapter 9: Abstract Generation
Chapter 10: SOC Encounter Place and Route
Chapter 11: Chip Assembly
Chapter 12: Design Example: TinyMIPS
Appendix A: Tool Administration
Appendix B: Highlights of the Tools
Appendix C: Tool and Startup Scripts
Appendix D: MOSIS SCMOS Rev8 Design Rules
Appendix E: Technology and Cell Libraries
Bibliography and Index


 


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