Title:	ECE/CS 6770 - Advanced Digital VLSI, Spring 2008
Instructor:	Ken Stevens, kstevens@ece.utah.edu, MEB 4506, 585-9176
Office Hours:	by appointment
Teaching Asst:	Vikas Vij, CADE lab after class and by appointment
TA E-Mail:	teach-cs6770@cs.utah.edu
Classes:	Tu/Th 3:40 - 5:00, WEB 112
Web Page:	www.eng.utah.edu/~kstevens/6770/6770.html
Prerequisites:	ECE/CS 5710/6710

This course addresses advanced issues in VLSI design, covering the following topics: design methodologies and IP design, CMOS circuit scaling, advanced logic circuit styles, noise sources and signal integrity in digital design, design techniques for dynamic and static power reduction, power supply issues, interconnect analysis, clocking and synchronization, process variation, and performance verification. Students are expected to complete a substantial design project as part of the course, which involves extensive use of CAD tools.

Students are required to have taken ECE/CS 5710/6710 (VLSI Design) or equivalent. The students must be familiar with elementary circuits, device physics and logic design, and should have experience with completing a medium scale CMOS design project, including timing, simulation, physical design and layout. Basic familiarity with Verilog, Synopsys, and Cadence design automation tools is assumed. Background in computer design and integrated circuits is very helpful.

Required Textbook:
A. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001

Additional Recommended Textbooks:

I. Sutherland, B. Sproull, D. Harris, Logic Effort - designing fast CMOS Circuits, Academic Press, 1999

M. Elrabaa, I. Abu-Khater, Advanced Low-Power Digital Circuit Techniques, Kluwer Academic Publishers, 1997

K. Bernstein, K. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak, N. Rohrer, High Speed CMOS Design Styles, Kluwer Academic Publishers, 1998 T. L Pillage, R. A. Rohrer, C. Visweswariah, Electronic Circuit and System Simulation, McGraw-Hill, 1994

D. Harris, Skew Tolerant Circuit Design, Morgan Kaufmann Publications, 2000

Lab assignments

In order to make students familiar with the design flow, there are three lab assignments. These assignments cover simple Verilog, simulation, synthesis, placement and routing, back-annotation, LVS and DRC exercises. Each Lab is due after one week and students are expected to work 6 to 8 hours per week.

A fourth lab assignment will be to research a circuit effect and report on how the effect can be tested, mitigated, and exacerbated in design.

Exams

The past two years we have administered one midterm exam, given at the middle of the semester and a final exam. The final exam is not cumulative and only covers class material covered after the midterm.

This year we will administer four examinations. Each exam will covering the technical areas covered in the class and the book for approximately one fourth of the course.

Course Project

Substantial design projects are completed by student teams. Teams can vary in size based on the size of the project. Preferred team size is 2 - 4 students.

Three design reviews will be required. Design review-1 will occur during the 6th week of the semester and design review-2 during the 12th week of the semester. The final design review (or the final design presentation and demo) is held at the end of the semester

Course Mailing Lists

You will need to sign up for the class mailing list. You can add yourself to the list and see archived messages by accessing the cs6770 mailman web site.

There are two mailing lists, cs6770@cs.utah.edu and teach-cs6770@cs.utah.edu. Mail sent to cs6770 goes to everyone in the class, whereas teach-cs6770 just goes to the instructor and TA. Please use discretion when sending messages to the entire class.

Disability:	If you have one that needs addressing contact the instructor immediately in the beginning of class.
Add/Drop Policy:	This class follows the University policy which is very strict.
Incomplete Policy:	Due to the project nature of the class, you cannot get an incomplete unless you have a documented medical or legal emergency or military call.

Extra Credit Policy: This class uses a Best of Breed philosophy in regard to the CAD tools, process technologies, and libraries that we teach in class. However, due to licensing restrictions, funding, training and maintenance time we have not yet been able to give full access to the best technologies in this course. We do hope to break break new ground with some CAD tools and process technologies this year and continue to improve our access to deep submicron technologies and CAD. Extra credit will be given to those who help with the process of improving knowledge and access to advanced technologies. One extra percentage grade point will be awarded for every 1-2 documented hours spent improving our tool setup, up to 10% extra grade points. Qualifying time includes helping with technology and tutorial setup and improvement, basic script creation for new tools, tool debugging, and helping other classmates with tool problems (outside standard usage issues). Documentation time is exempt, but required for the credit. For example, you could help figure out different options for running and analyzing SPICE results, providing scripts and cheatsheets for running FASTSCAN, setting up tools to work on other process technologies, etc. You will need to receive approval from the instructor for this extra credit, and the results must be disseminated to the entire class.

Class Schedule, reading assignments, and project assignments and due dates.

Short Syllabus with reading assignments.

Student Design Reviews and Project Report Requirements

Approximate detailed schedule for what we have covered in this course in the past.

The CAD tools that we currently have installed and documented are listed on our web page at http://www.eng.utah.edu/cad/.

Lab 1 Assignment due 19-Jan 11:59pm

• The c-code golden model with random number generation.
• C code for the simple golden model that implements a sequential data stream.
• The four scripts for running design compiler:
  • mult.dc: the top-level script.
  • common.dc: The common setup that links the library and cells. This uses the UofUDigital_v1_1 library.
  • timing.dc: Timing scripts.
  • namingrules.dc: Node naming restrictions and modification scripts.
  • makefile: A makefile for running your scripts.
  • An example mult.do script for running ModelSim to validate your design using tcl. You will also need to compile all of the UofU_Digital_v1_1 library cells into your WORK directory. You can do that with this ModelSim project file.
• These are the new scripts. They consist of two parts, the rtl optimization run and the design compiler runs. Each of these is launched from a shell script. The intention is to name the script after the top level cell being developed.
  • mult.cstr.tcl: This is the constraint (cstr) file that defines the clock period, etc.
  • namingrules.dc: This is the same file as the old scripts. It enforces consistent network and cell names.
  • mult.rtlopt.csh: This csh script launches design compiler. This will ensure your rtl is well formed, and will write it out for loading by the next script. Make sure the file is executable with chmod 755 mult.rtlopt.csh
  • mult.rtlopt.tcl: This is the actual script for generating correct rtl.
  • mult.dcopt.csh: This is the shell script for running the whole synthesis flow. Make sure it is executable!
  • mult.dcopt.tcl: This is the tcl script for running the full compilation.

Lab 2 Assignment, due 2-Feb 11:59pm

• BILBO Modules:
  • lfsr16.v
  • sa16.v
• Example scripts for place and route of multiplier module:
  • mult.tcl for UofU library
  • mult.conf for UofU library
  • multA.tcl for Artisan library (no physicals)
  • multA.conf for Artisan library (no physicals)
  • multUW.tcl for UW library
  • multUW.conf for UW library
• Full Chip structural model
  • chip.v

Lab 3 Assignment, due 23-Feb 11:59pm

Lab 4 Assignment, due 8-March 11:59pm

• Spice simulation netlist and control files:
  • The nand2.sp spice netlist
  • The nand2.control hspice control file
• Technology files:
  ami 500nm model, predictive 180nm model, predictive 65nm model, predictive 32nm model.

Following are the lecture notes and outside material that was covered during lectures.

Exam 1:

A useful paper on the correct usage of delays in verilog code.

Process Scaling

Scaling Trends

Logical Effort

Asynchronous Circuits and Systems

Logic Circuit Styles

Exam 3:

Circuit Timing Validation

Leakage and Power Reduction

Exam 4:

Interconnect and Inductance

Process Variation

Project Ideas

Final Project Reports from the 2008 course:

Better Hardware Noise
by Josef Spjut

Design of process invariant Delay Lock Loop (DLL)
by Manohar Nagaraju

Dynamic versus Static Logic in Asynchronous Pipelines
by Michael Diamond.

Four-Point FFT Processor; An Asynchronous/Synchronous Comparison
by Radhika Balasubramanian, Anil Kumar Reddy Palaparthi, Arun Tejusive Raghunath Rajan, and Trent Rolf.

Haar Wavelet Transform for Low Power Data Compression using Dynamic Body Biasing
by Bennion Redd and Toren Monson.

Leakage and Capacitance Optimized SCR Based ESD Protection Structures for Precision Analog IC Applications
by Tyler A. Day.

Linear Asynchronous and Synchronous FIFOs in Different Scaled Libraries
by Amany El Gouhary.

Modifying P/N Ratios for Optimum Performance
by Scott Brimley.

Final Project Reports from the 2007 course:
(partial set:)

Design of Asynchronous Interconnect Network for SoC
by Hosuk Han and Junbok You.

Desynchronization of a Processor
by Vikas Vij.

Final Project Reports from the 2006 course:

Application of Power-Management Techniques for Low Power Processor Design
by Sivaram Gopalakrishnan, Chris Condrat, and Elaine Ly.

Domino Static Gates
by Krishna Santhanam

Dynamic Voltage and Frequency Scaling in an Embedded Microcontroller SoC
by Nathaniel Gaskin, Amlan Ghosh, and Spencer Kellis

Feasibility of a Pass Transistor Logic Library for General Purpose ASIC Design
by Preston Thomson and Travis Johnson

Low-Power Digital Signal Processing for an Implantable Neural Recording System
by Paul Watkins

Point to point Communication System
by Omkar Iyer and Vamsi Mudarapu