ECE/CS 5960/6961
Relative Timed Asynchronous Design
Spring 2014

General Information:

Title: ECE/CS 5960/6961 - Relative Timed Asynchronous Design
Instructor: Ken Stevens, kstevens@ece.utah.edu, MEB 4506, 801-585-9176
Classes:Tue & Thu 2:00pm - 3:20pm, WEB-L 102
Office Hours:   by appointment
Web Page: www.eng.utah.edu/~kstevens/6961/
Teaching Asst:Shay Abbasi, email: shafagh.abbasi AT gmail DOT com
TA Hours:Upon request
Prerequisites:    Digital Design (3700/3710 or equiv.), VLSI or embedded systems (5710/6710, 5780 or equiv.)

Course Description:

This course will teach both the theory and art of asynchronous design. The focus of the course is on design; to understand and implement low power, high performance digital systems that don't use a clock for sequencing events. Asynchronous design differs significantly from traditional clocked design practices that are currently being taught and used. Therefore, to become an effective asynchronous digital designer, one first needs to establish a firm theoretical foundation of asynchronous design. The design component will employ the theory in creative ways to implement innovative low power and high performance design. The topics covered in this course will include theoretical asynchronous design classifications and circuit families, hazards, communication channels, formal representation of sequential designs, synthesis, formal verification of sequential protocols, relative timing, synchronization and concurrency, protocol families and equivalence classes, asynchronous design classes, pipelining, and creating design wins through asynchronous design approaches. The course will be very hands-on with numerous small to medium size projects with interactive discussion on design approaches and optimizations. There will be a midterm exam covering aspects of asynchronous theory and design. The graduate level section will require the review of a technical paper relating to asynchronous design.

This course requires that the student is already knowledgeable in traditional digital design, including the CAD tools employed for synthesis, timing validation, and place and route. Familiarity with digital design and CAD are aptly demonstrated by taking Digital VLSI design or Embedded Systems Design. The design work will focus on ASIC designs. Scripts for synthesis, place and route, and timing verification will be provided, and we will likely work on an advanced technology node.


Required Textbook:
None.
Handout materials will be provided in class, including a number of textbooks that will be provided.


Grading Policy:

Refer to the College of Engineering Guidelines for detail on appeals, disabilities, adding, and withdrawing from courses.

Incomplete Policy:   You can't get an incomplete unless you have a documented medical or legal emergency.
Add/Drop Policy: The standard University Policy is applied.
Disability: If you have a condition that merits consideration, you must contact the instructor at the beginning of the course.

Grades will be determined as follows:
Homework and Labs:      80%
Exam: 20%

Detailed Course Information:


Lab Assignments:

The CAD tools that we currently have installed and documented are listed on our web page at http://www.eng.utah.edu/cad/.



Lecture Notes:

Lecture notes and outside material may be posted here.


 

Useful Links:

See the Class Schedule for reading assignments.
 

I highly suggest you purchase these books:


 


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