I was a PhD student in the Department of Electrical and Computer Engineering at the University of Utah. I have completed my PhD in Aug 2008. I also have a Masters in Electrical Engineering from the University of Utah and Bachelors in Electronics and Communication Engineering from Sri Venkateswara College of Engineering (aka SVCE), India. 

I used to work as a research assistant in the Synthesis, SAT and Verification Group (SSVG) in the ECE dept. at the University of Utah. Specifically, my research was focused on high-level synthesis of arithmetic datapaths. More details about my PhD research can be found here. If you wish to download my publications, they are available here. 

Presently, I work in Formal verification techniques at Synopsys, Inc. 

Please feel free to contact me if you have any questions or comments.