UofU
Electrical and Computer Engineering Department

Homework

Homework is due by 5 pm. on due date.

Please note that the answers given may be prone to errors.

Homework Modifications Answers Due Date

Problem Set #1

Solution

Semilog Graph Paper(4 to a page)

Semilog Graph Paper (2 to a page)

1.  Vo/Vg=5.9, Rth=40, Vth=5.9Vg; 2.a.  11.8, b.  29.5, c.  5.9sin(10t); 3.Vo/V1=0.833/(1+0.05s) Jan. 13

Problem Set #2

Solution

  1.  Low pass filter with bandwidth up to 10 rad/sec.  4.  Bandwidth from 10 to 1000 rad/sec.  5. Bandwidth from 1 to 1k rad/sec.  6. ID1=1mA, ID2=0, Vo=2.7V  7.  ID1=18mA, ID2=0, Vo=-9.3V  8.  Id_total=18m+-1mA  9.  ID1=0, ID2=34mA, Vo=-19.3, Id2_total=34m+-989microA   Jan. 27

Problem Set #3

Solution

Assume all capacitors act as an "open" for DC analysis. 2.  VB=0, VE=-0.7, VC=4, IB=19.3micro, IC=1.93m, IE=1.95m; 3.  VB=8.5, VE=7.8, VC=9.2, IB=77micro, IC=7.69m, IE=7.76m; 4.  VB=-8.26, VE=-7.6, VC=-9.13, IB=176micro, IC=17.4m, IE=17.6m; 5.  VB=0.96, VE=1.66, VC=-2.6, IB=4micro, IE=0.4m, IC=0.396m; 6.  VB=-0.099, VE=-.799, VC=13.02, IB=19.8micro, IC=1.98m, IE=2m; 7. IB1=6.8n, IB2=IE1=683n, IB3=IE2=69micro, IC3=IE3=7m, VE3=13, VB3=13.7, VB2=14.4, VC1=15, VB1=15; 8.  VC=2.85, VB=0.25, VE=-0.45, IE=1.55m, IB=15.35micro, IC=1.53m; 9.  VB=-0.3, VC=2.3, VE=-1, IE=7.46m, IB=73.8micro, IC=7.39m; 10.  VE=-6.8, VB=-6.1, VC= 8.4, IE=1.59m, IB=15.7micro, IC=1.57m          Feb. 10

Problem Set #4

Solution

  1.  Rc=302 ohms, 4.b.  beta_forced=10, c.  Rc<2030; 5.b.  beta_forced=9; 6.  beta_forced=27.3; 7.c.  Saturation    Feb. 19

Problem Set #5

Solution

All AC Sweeps are on a logarithm scale.
6.  add 1pF to the value list
.
3.  Vout/Vin=1.51; Rin=9630, Rout=2k; 4.gain=1.5(similar to 3a); Rin=10k; Rout=2k; 5.  b.  C1 effects the starting value for the bandwidth of the circuit.  c.  The trace where the -3dB is less than 20Hz; 6.b.  The 1pF value creates the first pole too high for the circuit to be able to amplify.  c.  The value that has the starting value less than 20Hz will be acceptable; 7.  They are the same.  The capacitors are blocking any DC effect on the biasing of the circuit.  gain=18V/V.  8.  hand analysis:  gain=17.3V/V, Rin=3400, Rout=2k; 9.  Vout/Vin=1.5V/V, Rin=440, Rout=2k; 10.  gain=877mV/V, Rin=9.5k, Rout=36. March 3

Problem Set #6

Solution

  1.  IE1=1.84m, IB1=18.2u, IC1=1.82m, VB1=-2.46, VE1=-3.16, VC1=1.34, IB2=9.9u, IE2=1m, IC2=0.99m, VB2=2.98, VE2=2.28, VC2=4; VIMAX=0.198V; 2.  IE1=1m, IB1=9.9u, IC1=0.99m, VB1=3.09, VE1=2.4, VC1=4.6, IE2=10m, IB2=99.9u, IC2=9.99m, VB2=1.05, VE2=0.35, VC2=2.01; VIMAX=0.192V; 3.  Rin=23,793, Rout=20k, Vo/Vsig=0.86; 4.  Rin=337,000, Rout=313, Vo/Vsig=-4; 7.  IB=10m, IC=105m, Bforced=10.5, RB<10k; 8.  IB=1m, IC=9.8m, Bforced=9.8, RB<46k; 9.  Rin=1732, Rout=118, Vo/Vsig=-243; 10. Rin=105,100, Rout=10k, Vo/Vsig=-480.5 March 17

Problem Set #7

Solution

  2.a. uCox(W/L)=200micro, Vt=1; b.  uCox(W/L)=400micro, Vt=-1.5; c.  uCox(W/L)=400micro, Vt=-1; d.  uCox(W/L)=100micro, Vt=0.8 (the bottom case is triode.)  6 and 7.  V1=-4, V2=2, V3=3.41, V4=4, V5=-5, V6=6, V7=2 a. 3.01k, V2=2.04, V1=-4.01;  b. 6.65k, V3=3.41; c.  3.01k, V4=4.01, V5=-5.03; d.  1k, V6=6, V7=2; 8.  VGS=3, VS2=4, ID=9, VD2=9; 9.  VGS1=2 or ID1=1m, Vs1=0, ID=4m, VD2=4.5; 10.  gm=1.9mA/V^2
March 31

Problem Set #8

Solution

  3.  Rin=5M, Rout=91, Vo/Vsig=-1, 4.  Rin=30k, Rout=238, Vo/Vsig=-6.35; 5.  Rin=1M, Rout=4k, Vo/VI=-4;  6.  I1=0, IS=1m, VG2=9V, VS2=3.75, VS1=-4, Vs2_total= 3.75-8msin(20t); 7.  I1=0, IS=1.4m, Vs1=-2.7, VG2=3.6, VS2=0.6; 8.  Rin=60k, Rout=20,548, Vo/Vsig= -389(gm1=80m) or -1231(gm1=.253)  April 7

Problem Set #9

Solution

4.b.  R3=100k, R1=R2=10k  1 and 2  R placed at + terminal.  3.  a.  4, b.  3MHz, c.  63.7kHz, d.  8mV, e.  16mV, f.  R at + terminal=2.4K; 4.  b.  80KHz, c.  105mVpeak, d.  R at + terminal; 5.  a.  20, b.  4MHz, 6.  a.  max=83mV, min=43mV, b.  R at + terminal.  7.  -(Vs+isR1)R4/(R1+R3), 8.  I1=0, Is=16m, VG2=4V, VS2=-1V, VS1=-2V; 9.  Won't be 0.1V ever.  10.  Rin=30,500, Vo/Vsig=-.97V/V  April 14