Ken Stevens

  • Phone: 801-585-9176
  • Email:
  • Office: MEB 2254

VLSI, asynchronous circuit design and architecture, timing analysis, and formal verification

Priyank Kalla

VLSI systems: automated synthesis and optimization, validation and verification of digital VLSI systems, including: formal verification of RTL descriptions, new techniques to guide CNF-SAT search, using Groebner's proof systems for simplification of design verification and SAT solving, and design automation for optic/photonic logic

Pierre-Emmanuel Gaillardon

  • Phone: 801-585-3422
  • Email:
  • Office: SMBB 3745

Development of reconfigurable logic architectures and digital circuits exploiting emerging device technologies and novel EDA techniques.