Pierre-Emmanuel Gaillardon, assistant professor of electrical and computer engineering at the University of Utah, was awarded close to $2 million over four years to lead two projects for the Defense Advanced Research Projects Agency (DARPA)’s new Electronics Resurgence Initiative (ERI) “Page 3” programs. Gaillardon and the rest of the awardees were announced on Monday, July 23, 2018 at the first annual ERI Summit in San Francisco, California.
The ERI aims to overcome the imminent roadblocks that will limit the growth of electronics capacities and computing capabilities. “Page 3” is in reference to the seminal 1965 paper by Gordon Moore, a pioneer of the “microelectronics revolution.” In his paper, Moore predicted that reducing the size of transistors essential for electronics would improve their performance. Now, transistors have become so small that we’re hitting the limits of physics.
“Modern transistors are only 70-atoms wide— it is a lot smaller than a virus,” said Gaillardon. “Very soon, we will be stuck and won’t scale any smaller.”
On page 3 of the paper, Moore listed the ways to get beyond the limits of transistor size: materials and integration, architecture and design. Gaillardon will lead two projects under the design category.
The first project, A learning-based oracle for logic optimization, aims to use machine-learning to properly guide the logic optimization process and help create more efficient digital circuits. This project is funded by ERI’s Intelligent Design of Electronic Assets (IDEA) program, which has a goal to create a hardware compiler capable of automatically building complex systems from a user-intent description language with no human in the loop.
“The program idea is to create an open-source hardware compiler, where people get all of the stuff they need to create very complex hardware systems without the need for a high level of expertise,” said Gaillardon. “There are lots of open source compilers for software, but almost nothing for hardware.”
The second project, entitled An automatic IP Generator for Customizable FPGA Architecture,aims to create open source high-quality FPGAs.
“FPGAs are circuits that you can reconfigure to implement any type of circuit, sort of the “stem cells” of integrated circuits. Get the “stem cells” and do whatever you want with that,” said Gaillardon.
This project is part of the Posh Open Source Hardware (POSH) program whose goal is to foster an eco-system of high-quality open source IPs to speed up the development process of complex system-on-chips.
“A lot of big companies are developing hardware, but it is all proprietary, as such, the macro-ecosystem is not evolving. There’s a big cost of entry in designing hardware systems. DARPA’s goal to create an open source hardware environment that everyone can improve is to ignite a vibrant community similar to what the software world experiences,” said Gaillardon.